The present invention relates in general to a semiconductor device and in particular to a semiconductor device incorporating a gate voltage testkey for selectively programming isolation transistor gate voltage.
DRAM memory has enjoyed popular success over other types of memory technology because of its low cost and simple memory cell layout which promotes scalability. A DRAM memory cell is capable of storing one bit of information, and is constructed using only one memory cell transistor and one memory cell capacitor. As such, this memory cell is often referred to as a one-transistor one-capacitor (1T1C) cell. A collection of memory cells are grouped together in bitlines and wordlines, forming a memory array.
While device density in DRAM memory is limited by the resolution capability of available photolithographic equipment, it is also limited by the area consumed by each of the memory cells. Referring to FIG. 1, a memory structure 10 is comprised of a plurality of memory cells 12. As identified herein, the minimum area of a memory cell 12 is defined with reference to a feature dimension (F) which refers to the dimension that is half the wordline WL pitch (width plus space) or half the digitline DL pitch (width plus space). To illustrate the determination of cell area, a box is drawn around the memory cell 12. Along the horizontal axis H of the memory cell 12, the box includes one-half digitline contact feature 14, one wordline feature 16, one capacitor feature 18 and one-half field oxide feature 20, totaling three features. Along the vertical axis V of the memory cell 12, the box contains one half field oxide feature 22, one active area feature 24, and a second half oxide feature 26 totaling two features. The structure of the memory cell 12 results in its area being 3F.multidot.2F or 6FSupp2. To conserve space on a die, memory cell pairs 28 are defined by adjacent memory cells 12 that share a single bitline contact 30.
While the 6 Fsupp2 array may be implemented as an open bitline as well as a folded bitline, early memory devices incorporated the open bitline configuration. In the open bitline architecture, each wordline connects to memory cell transistors on every bitline. This is sometimes referred to as a crosspoint style array. Referring to FIG. 2, a memory structure 100 is illustrated for an open digitline architecture. The memory structure 100 includes a plurality of memory cells 102. Each memory cell 102 is comprised of a capacitor 104, having a common node 106 biased at a voltage of Vcc/2 volts. The capacitor 104 typically represents a binary logic level one by a charge of +Vcc/2 volts, and a binary logic level zero by a charge of xe2x88x92Vcc/2 volts. Each memory cell 102 is further comprised of a transistor 108 having a first source/drain region 110, a second source/drain region 112, and a gate 114. The gate 114 of each transistor 108 connects to a wordline (WL) 116, 118, 120, 122, 124 and 126. Further, the first source/drain region 110 of each transistor 108 connects to a bitline (BL) 128.
As demands for higher capacity memory devices continue to increase, memory cells are placed closer together. However, where memory cells of a conventional 6 Fsupp2 array are packed too closely, adjacent memory cells may be affected by subthreshold leakage. Excessive subthreshold leakage may affect data integrity. In an attempt to resolve the problems that are attributable to the conventional 6 Fsupp2 array, the industry adopted an 8 Fsupp2 array where improved noise performance is realized by providing a twisted configuration. The 8 Fsupp2 memory array is created by tiling a selected quantity of memory cells together such that memory cells along a given bitline do not share a common wordline and such that memory cells along a common wordline do not share a common bitline. Any given wordline forms a memory cell transistor on alternating bitlines. This structure allows the formation of bitline pairs and ensures that wordline activation enables transistors only on alternate bitlines. Further, the 8 Fsupp2 provides improved noise performance, which is derived from the adjacency of true and complement bitlines and the capability to twist these bitline pairs. However, since the wordlines have to pass alternate memory cells as field poly, the size is increased by approximately 25%, or by 2 features. As such, the 8 Fsupp2 array does not provide the same degree of packing density seen in the 6 Fsupp2 array described above. As the demand for memory devices with larger capacity continues to increase, the larger array size provided by the 8 Fsupp2 array become a limiting factor.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a 6 Fsupp2 area array with improved subthreshold leakage characteristics, which allows for a higher packing density thus more densely populated memories.
The present invention overcomes the disadvantages of previously known 6 Fsupp2 array architectures by providing a programmable gate voltage to minimize subthreshold leakage of an isolation transistor positioned between adjacent memory cells.
The memory cell is thoroughly tested using a testkey device, which is capable of testing different isolation gate voltages on the fly, without the need to create a reticle to change the gate voltage. The testkey is such that a fair comparison of data collected from the same array space can be realized. Further, upon determining that the measured subthreshold leakage for a particular bit is excessive, the isolation transistor gate can be permanently changed from ground, or zero volts to the back bias voltage (Vbb), or some other voltage more negative than ground to effectively shut the transistor off harder. The testkey may selectively test alternative negative potentials, until the subthreshold leakage is brought within satisfactory parameters. Once the required isolation gate potential has been determined, it may optionally be permanently programmed to that potential, using an antifuse device.
In a first embodiment of the present invention, a memory device has an array of storage cells having a plurality of selectively addressable memory cells coupled to a bitline, and isolation devices positioned to prevent leakage between the plurality of selectively addressable memory cells, each of the isolation devices having an isolation control. A test circuit is coupled to the array of storage cells, and is capable of determining characteristics of the isolation devices. A translator is coupled to the test circuit, and has a bias control coupled to each of the isolation controls. The translator is programmable to provide one of at least two bias signals to the isolation controls.
Preferably, the isolation device comprises an isolation transistor, and the isolation control comprises a gate of the isolation transistor. Under this arrangement, the translator bias control is coupled to the gate of the isolation transistor, and the translator is programmable to provide one of at least two voltages to the gate of the isolation transistors, each of the at least two voltages are biased to turn off the isolation transistors. The present embodiment can be realized in a 6 Fsupp2 array, in an open or closed bitline architecture where the array of storage cells further comprises a plurality of bitlines, and the plurality of selectively addressable memory cells further comprises a plurality of adjacent storage cell pairs connected to each of the plurality of bitlines, and the isolation transistors are positioned to provide isolation between each of the plurality of adjacent storage cell pairs.
While the chip is in the test mode, the testkey is capable of determining the isolation gate voltage needed for the isolation transistors to remain off. When the chip is not being tested, a device such as an antifuse device coupled to the translator and to the test circuit can be used to permanently select one of the at least two bias signals.
In a second embodiment of the present invention, an array of storage cells have a plurality of bitlines, a plurality of adjacent storage bit pairs coupled to each of the plurality bitlines, and isolation transistors positioned to prevent leakage between each of the plurality of adjacent storage bit pairs. A test circuit is coupled to the array of storage cells, which is used to determine the characteristics of the isolation transistors, including the leakage of the isolation transistors. A translator is coupled to the test circuit, and has a bias control coupled to each of the gates of the isolation transistors. The translator is programmable to provide one of at least two voltages to the gate of the isolation transistors, each of the at least two voltages biased to turn off the isolation transistors. An antifuse device may optionally be coupled to the translator. The antifuse device is programmable to select one of the at least two bias signals when the memory device is not in a test mode.
In yet another embodiment of the present invention, an array of storage cells have a plurality of bitlines, a plurality of adjacent storage bit pairs coupled to each of the plurality bitlines, and isolation transistors positioned to prevent leakage between each of the plurality of adjacent storage bit pairs. A test circuit is coupled to the array of storage cells, and is used to determine the characteristics of the isolation transistors. A translator is coupled to the test circuit, and has a bias control coupled to each of the gates of the isolation transistors. The translator is programmable to provide one of at least two voltages to the gate of the isolation transistors, each of the at least two voltages biased to turn off the isolation transistors. Further, an antifuse device is coupled to the translator, the antifuse device programmable to select one of the at least two bias signals. The circuit is configured such that the bias control of the translator is adjustable by the test circuit while the memory device is in a test mode, and the bias control is held at a fixed one of the at least two voltages when the memory device is out of the test mode by the antifuse.
In yet another embodiment of the present invention, an isolation gate biasing circuit in an embedded DRAM has a test circuit programmable to send, receive and compare at least one data test signal to a plurality of addressable memory cells, the plurality of addressable memory cells having isolation transistors between adjacent ones of the plurality of addressable memory cells, the test circuit used to determine isolation transistor characteristics. Further, a translator is coupled to the test circuit and is programmable to bias a gate on each of the isolation transistors to any one of at least two voltages, each of the at least two voltages biased to turn off the isolation transistors. Preferably, the test circuit is operable to program the translator to bias the gates of the isolation transistors to a select one of the at least two voltages on the fly.
The test circuit further comprises a test mode configured to allow the test circuit to program the translator only when the test mode is active. Optionally, the isolation gate biasing circuit further has an antifuse array coupled to the translator, the antifuse array being permanently programmable such that, once programmed, the translator is permanently programmed to a select one of the at least two voltages.
In yet another embodiment of the present invention, an isolation gate biasing circuit in an embedded DRAM comprises a test circuit programmable to send, receive and compare at least one data test signal to a plurality of addressable memory cells. The plurality of addressable memory cells have isolation transistors between adjacent ones of the plurality of addressable memory cells, and the test circuit is capable of determining isolation transistor leakage. A translator is programmable to bias a gate on each of the isolation transistors to any one of at least two voltages, each of the at least two voltages biased to turn off the isolation transistors, and a programmable antifuse array is coupled to the translator. The translator is programmable by the test circuit on the fly, while the isolation gate biasing circuit is in a test mode, and the translator is controlled by the antifuse array to bias the isolation transistors at a fixed one of the at least two voltages when the isolation gate biasing circuit is out of the test mode.
In a further embodiment of the present invention, a method of reducing subthreshold leakage in an isolation transistor positioned to prevent leakage between adjacent cells in an open digitline memory architecture comprises the steps of setting an isolation gate voltage to a first voltage. The next step involves applying the isolation gate voltage to a gate of the isolation transistor, measuring a subthreshold leakage of the isolation transistor and comparing the subthreshold leakage to a desired subthreshold leakage. The next step includes setting the isolation gate voltage to a second voltage if the subthreshold leakage is greater than the desired subthreshold leakage.
The method of reducing subthreshold leakage may optionally include the steps of re-measuring the subthreshold leakage if the isolation gate voltage is set to the second voltage, and comparing the re-measured subthreshold leakage to the desired subthreshold leakage. The chip may provide a failure signal if the re-measured subthreshold leakage exceeds the desired subthreshold leakage. Further, the step of permanently programming the isolation gate voltage when the subthreshold leakage is less than the desired subthreshold leakage may be realized. Preferably, the first voltage is zero volts, and the second voltage is a back bias voltage, the second voltage being more negative than the first voltage. The first and second voltages are set using a translator, and using a testkey to control the translator and further to measure the subthreshold leakage.
In yet another embodiment of the present invention, a semiconductor circuit comprises a first transistor having a gate, a first source/drain region, and a second source/drain region, a second transistor having a gate, a first source/drain region, and a second source/drain region and a first isolation transistor having a gate, a first source/drain region, and a second source/drain region. A first bitline is coupled to the first source/drain region of the first transistor, while a first wordline coupled to the gate of the first transistor. A first capacitor couples a first reference voltage to the second source/drain region of the first transistor. The first source/drain region of the isolation transistor is coupled to the second source/drain region of the first transistor, while the second source/drain region of the isolation transistor is coupled to the first source/drain region of the second transistor. A second capacitor couples the first reference voltage to the first source/drain region of the second transistor. The first bitline is further coupled to the second source/drain region of the second transistor, and a second wordline is coupled to the gate of the second transistor. A translator is coupled to the gate of the first isolation transistor. The translator is programmable to provide one of at least two voltages to the gate of the first isolation transistor, each of the at least two voltages biased to turn off the first isolation transistor.
The first isolation transistor is preferably an n-channel transistor. Under this arrangement, it is preferable that the at least two voltages of the translator further comprise a first voltage of zero volts, and at least one negative voltage. More preferably, the at least two voltages of the translator further comprise a first voltage of zero volts, and a second voltage equal to the semiconductor circuit back bias voltage. Optionally, the at least two voltages of the translator may further comprise a first voltage of zero volts, and a second voltage equal to the semiconductor circuit back bias voltage, and at least one voltage between the first voltage and the second voltage.
The semiconductor circuit may optionally include a test mode logic coupled to the translator for selectively programming the at least two voltages of the translator, and may further include at least one antifuse coupled to the translator, the at least one antifuse capable of permanently programming the translator.
In yet another embodiment of the present invention, a semiconductor circuit comprises a first transistor having a gate, a first source/drain region, and a second source/drain region, a second transistor having a gate, a first source/drain region, and a second source/drain region and a first isolation transistor having a gate, a first source/drain region, and a second source/drain region, the first isolation transistor being an n-channel transistor. A first bitline is coupled to the first source/drain region of the first transistor, a first wordline is coupled to the gate of the first transistor, and a first capacitor couples a first reference voltage to the second source/drain region of the first transistor. The first source/drain region of the isolation transistor is coupled to the second source/drain region of the first transistor, and the second source/drain region of the isolation transistor is coupled to the first source/drain region of the second transistor. A second capacitor couples the first reference voltage to the first source/drain region of the second transistor, the first bitline is coupled to the second source/drain region of the second transistor, and a second wordline is coupled to the gate of the second transistor. A translator is coupled to the gate of the first isolation transistor, the translator being programmable to provide one of at least two voltages to the gate of the first isolation transistor, each of the at least two voltages biased to turn off the first isolation transistor. Further, a testkey logic circuit is coupled to the translator for selectively programming the at least two voltages of the translator when the semiconductor circuit is in a test mode and at least one antifuse is coupled to the translator. The at least one antifuse selects one of the at least two voltages when the semiconductor circuit is out of the test mode. Under this arrangement, the at least two voltages of the translator further comprise a first voltage of zero volts, and a second voltage equal to the semiconductor circuit back bias voltage.
In another embodiment of the present invention, a semiconductor chip has an open bitline memory array. The open bitline memory array has a plurality of bitlines, a plurality of memory cell pairs coupled to each of the plurality of bitlines, an isolation transistor positioned to prevent leakage between adjacent ones of the plurality of memory cell pairs. A testkey is coupled to the open bitline memory array capable of determining isolation leakage, and a translator is coupled to each of the gates of the isolation transistors, the translator providing one of at least two voltages to the gates, each of the at least two voltages biased to turn off the isolation transistors. The testkey is capable of programming the translator between any one of the at least two voltages on the fly, while the semiconductor chip is in a test mode, and the testkey programs the translator to a fixed one of the at least two voltages while the semiconductor chip is out of the test mode.
Preferably, the isolation transistors are n-channel isolation transistors, and the at least two voltages comprises a first voltage of zero volts, and a second voltage of a back bias voltage, the back bias voltage being more negative than zero volts. Optionally, the at least two voltages comprises a first voltage of zero volts, a second voltage of a back bias voltage, the back bias voltage being more negative than zero volts, and at least one voltage between the first and second voltages. Each of the gates of the isolation transistors are connected to any one of the at least two voltages from the translator. The isolation transistor gate voltages need not be identical throughout the memory array.
In yet another embodiment of the present invention, a computer system is provided, the computer system comprising a processor, an input device coupled to the processor, an output device coupled to the processor, an address bus coupled to the processor, a data bus coupled to the processor and a memory device coupled to the processor. The memory device includes a first bitline, a first wordline, and a second wordline. A first memory cell has a first transistor having a gate coupled to the first wordline, a first source/drain region coupled to the first bitline, and a second source/drain region. A first capacitor couples a first reference voltage to the second source/drain region of the first transistor. A second memory cell has a second transistor having a gate coupled to the second wordline, a first source/drain region coupled to the first bitline, and a second source/drain region. A second capacitor couples the first reference voltage to the second source/drain region of the second transistor. A first isolation transistor has a gate, a first source/drain region coupled to the second source/drain region of the first transistor, and a second source/drain region coupled to the second source/drain region of the second transistor. A translator has a translator output coupled to the gate of the first isolation transistor, and a test circuit is coupled to the translator. The test circuit is arranged to program the translator to provide one of at least two voltages to the translator output, each of the at least two voltages biased to turn off the first isolation transistor.